1. Field
The present invention relates to a method for fabricating a nonvolatile memory device, and more particularly, to a method for fabricating a nonvolatile memory device including a plurality of memory cells stacked vertically over a substrate.
2. Description of the Related Art
A nonvolatile memory device is a memory device which maintains data stored therein although power supply is cut off. Currently, various nonvolatile memory devices, for example, NAND Flash memory and the like are widely used.
Recently, as the improvement in integration degree of nonvolatile memory devices having a 2D structure in which memory cells are formed as a single layer over a semiconductor substrate approaches the limit, a nonvolatile memory device having a 3D structure in which a plurality of memory cells are stacked vertically over a silicon substrate has been proposed.
The 3D nonvolatile memory device may be fabricated by the following series of steps of: alternately stacking a plurality of interlayer dielectric layers and a plurality of sacrificial layers over a substrate; selectively etching the stacked structure to form a channel hole passing through the stacked structure; forming a memory layer and a channel in the channel hole; and replacing the sacrificial layer with a gate electrode layer. Alternatively, the 3D nonvolatile memory device may be fabricated by the following series of steps of: alternately stacking a plurality of interlayer dielectric layers and a plurality of gate electrode layers over a substrate; selectively etching the stacked structure to form a channel hole passing through the stacked structure; and forming a memory layer and a channel in the channel hole. At this time, one gate electrode layer and the memory layer and the channel, which are contacted with the gate electrode layer, form a unit memory cell.
Here, the channel hole may have a constant diameter regardless of the height. In other words, the sidewalls of the channel hole may have a vertical profile. This is because the channel hole must have a constant diameter to uniformly secure the characteristics of the memory cells.
However, when the stacked structure of the interlayer dielectric layers and the sacrificial layers or the stacked structure of the interlayer dielectric layers and the gate electrode layers is etched to form the channel hole, it may be difficult to form a channel hole having a vertical profile. This is because the interlayer dielectric layer and the sacrificial layer or the interlayer dielectric layer and the gate electrode layer are formed of materials having different etch rates from each other. Such a concern may become more serious as the height of the stacked structure is increased to improve the integration degree of the device.